1. Field of the Invention
The invention relates to the design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for verifying a large design of an integrated circuit (IC) layout, by verification of small regions of the layout, and combination of the results.
2. Related Art
A computer programmed with appropriate software (called layout verification tool) is normally used to verify that an overall design of an integrated circuit (IC) chip conforms to certain predetermined tolerances that are required by a process to be used in fabricating the chip. Examples of such a layout verification tool include (1) HERCULES software available from Synopsys, Inc. 700 East Middlefield Road, Mountain View, Calif. 94043, and web site www.synopsys.com, (2) VAMPIRE software available from Cadence Design Systems, Inc, 555 River Oaks Parkway, San Jose, Calif. 95134, and web site www.cadence.com, and (3) CALIBRE software available from Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, Oreg., 97070, and web site www.mentor.com.
Tolerances for the process that is to be used to fabricate the IC chip are often specified by IC chip designers in the form of “rules” that are used by the layout verification tool to confirm that a chip's design can be manufactured by an IC fabrication process (in an operation called “design rule check” (DRC) or “mask rule check” (MRC), depending on whether or not the design has been Optical Proximity Corrected). Examples of rules (also called “verification rules”) to be used in checking an IC design include: (1) minimum width of a trace (i.e. line) or other feature, (2) minimum spacing between elements of a circuit (e.g. between adjacent lines), (3) minimum width of notches and (4) checks for acute angles.
Verification rules are normally stored in a predetermined sequence (e.g. in a computer file) commonly called a “runset” (also called “rule set,” “rule file,” “rule deck,” or “rule scripts”). The runset is supplied as input to the layout verification tool, for use in checking if a design conforms to rules in the runset. The rules may be applied to the entire layout of the IC design, if the design is sufficiently small and the layout verification tool is executing in a computer that has sufficient resources (e.g. memory and computation power).
However, as IC designs get bigger, a single computer does not have sufficient memory and/or computation power to verify and synthesize an entire mask layout before manufacture. Hence, a large IC design (illustrated in FIG. 1A) is partitioned into multiple regions (two regions are illustrated in FIG. 1B) with the layout verification tool being applied to each region independent of another region (as illustrated in FIGS. 1C and 1D).
Execution of a runset on each individual region, independent of another individual region, creates artifacts when shapes cross a boundary between regions. In the illustration of FIG. 1C, a rule applicable to shapes that interact is not applied to rectangle 101, although rectangle 101 interacts with rectangle 102 as shown in FIG. 1D.
Such artifacts may be avoided by manually partitioning a large layout into multiple regions while taking care to avoid cutting a shape. However, manual partitioning is labor intensive, and there is no known method to ensure that satisfactory partitions are made of a large and complex IC layout.
One prior art method for reducing such artifacts is described in U.S. Pat. No. 6,077,310 granted to Yamamoto et al. on Jun. 20, 2000 entitled “Optical Proximity Correction System”, which is incorporated by reference herein in its entirety. This patent describes the conventional method as shown in FIG. 1E and the use of overlapping regions at the boundaries of a region-under-verification in FIG. 1F. See Yamamoto's column 7 lines 28-44.
As shown in FIG. 1F, Yamamoto adds a buffer area B to the periphery of a to-be-corrected area A. The to-be-corrected area A and the buffer area B are combined to form an area C on which calculations for proximity correction are performed. In FIG. 1E, c is an already corrected optical proximity effect calculation area, b is the buffer area of c, and a is the corrected solution of the to-be-corrected area. Note that a buffer area is also called “ambit” in some prior art systems use a similar technique in rule checking (DRC or MRC).
The inventor of the current patent application has recognized that prior art methods using buffer areas result in two types of problems, a global scope problem and a local scope problem as discussed next. Specifically, in a global scope problem illustrated in FIG. 1C, when verifying the upper region of the IC design, rectangle 101 that spans across two regions may still not be selected if the buffer area (or ambit) is not sufficiently wide to include a portion of rectangle 102.
In a local scope problem illustrated in FIGS. 1G-1L, initially there are two rectangles 111 and 112 in the upper region and two rectangles 113 and 114 in the lower region, as shown in FIG. 1G, and the space between rectangles is marked as 115, 116 and 117 as shown in FIG. 1H. Note that FIGS. 1I and 1J illustrate the independent and individual checking of the upper region and the lower region respectively, while using boundary areas. Next, referring to FIG. 1K, the space between rectangles 115, 116 and 117 is marked again, as 118 and 119 shown in FIG. 1L. Therefore, at this stage, in the upper region there is one rectangle 118.
Hence a check for space between two rectangles at this stage, when applied to only the upper region results in an empty set. Similarly in verifying the lower region as well, as there is only one rectangle 119 that is left, just before the last rule in the runset is executed, the space between rectangles is an empty set also. Therefore, a space 120 which is in fact located between rectangles 117 and 118 is not detected when performing verification in each of the upper region and the lower region independently, even though using ambit.
In some instances, it may be possible for an IC chip designer to prepare a runset that contains commands to overcome the above-described problems, but such an “intelligent” runset is not generic across IC designs, and also not scaleable (because manual customization is required).